Microelectronic devices such as semiconductor chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself. To facilitate ease in handling, testing and other processes associated with product manufacturing, semiconductor chips are typically provided in microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer or a cell phone.
Certain microelectronic device chips require a protective element, e.g., a cover over all or part of the front surface. For example, chips referred to as surface acoustic wave or “SAW” chips incorporate acoustically-active regions on their front surfaces, which must be protected from physical and chemical damage. Similarly, microelectromechanical systems or “MEMS” chips may include microscopic electromechanical devices such as microphone transducers or micromechanical devices such as sensors that require protection. See, e.g., U.S. Pat. No. 5,610,431 to Martin. In any case, the covers used for MEMS and SAW chips are generally spaced from the front surface of the chip to an open gas-filled or vacuum void beneath the cover in the active area, so that the cover does not touch the acoustical or mechanical elements.
In addition, certain electro-optical chips such as optical sensing chips and light-emitting chips have photosensitive elements which also must be protected by a cover. Voltage controlled oscillators (VCOs) and other radio frequency (RF) device sometimes also require a cover to be placed over the active area.
Miniature SAW devices can be made in the form of a wafer, and provided with electrically conductive contacts used to make electrical connections between the SAW device and other circuit elements. In addition, the devices can be provided with covers while still in wafer form. The wafer may then severed to provide individual devices. For example, as described in U.S. Pat. No. 6,429,511 a cover wafer formed from a material such as silicon can be treated to form a large number of hollow projections and then bonded to the top surface of the active material wafer, with the hollow projections facing toward the active wafer. After bonding, the cover wafer is polished to remove the material of the cover wafer close to the projections. This leaves the projections in place as covers on the active material wafer, and thus forms a composite wafer with the active region of each SAW device covered by a cover. Such a composite wafer can be severed to form individual units.
Similarly, U.S. patent application Ser. No. 10/949,674, entitled “Structure and Method of Making Capped Chips Having Vertical Interconnects,” filed Sep. 24, 2004, inventors Humpston, Tuckerman, McWilliams, Haba, and Mitchell, describes wafer-level methods for producing capped chips. The capped chips have electrical interconnects made from elements that extend from contacts of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the contacts, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.
Additional wafer-level packages are described in U.S. Pat. No. 6,326,697 to Farnworth.
As alluded to above, it has been proposed that microelectronic packages be formed as a wafer-level assembly to improve productivity and reduce costs associated with microelectronic manufacturing. Wafer-level assemblies allow a plurality of devices in the form of a wafer to be packaged with one or more covers. As a result, a unitary wafer-level structure is formed. Once formed, the wafer-level structure may then be diced and separated into individual packages.
Depending on the configuration and other requirements of microelectronic packaging involving a microelectronic device and a cover, different cover materials may be used. For example, when the coefficient of thermal expansion (CTE) for the device differs significantly from the CTE for the cover, however, the device and the cover will expand and contract at different rates. As described in more detail below, problems associated with CTE mismatch between the wafer and the cover is exacerbated due to the size of the wafer-level assembly. Thus, wafer-level manufacturing of microelectronic packages typically requires exceptionally close matching of device and substrate CTE. For example, as described in U.S. patent application Ser. No. 10/949,674, when microelectronic devices made from silicon are packaged with a cover in a wafer-level manufacturing process, silicon or a glass having a CTE similar to that of silicon may be used to form covers. Similarly, as described in U.S. Pat. No. 6,429,511 to Ruby et al. a silicon cover may be provided over a silicon wafer.
Accordingly, there exist opportunities to provide alternatives and improved technologies to overcome the problems associated with microelectronic packages having a cavity located between covers and devices, particularly those technologies that lend themselves to wafer-level manufacturing of packages and those technologies that solve CTE mismatch problems between covers and devices.